Jeremy Bennett & Simon Cook 2016-11-28T06:16:19+00:00

Embecosm

Name: Jeremy Bennett (Chief Executive),Simon Cook (Compiler Engineer)
Tool: The Adpateva Epiphany Processor
Ultra-low power High Performance Computing

Description:  Epiphany is an ultra-low power multicore floating-point co-processor. The standard processor has 16 cores, delivering a total of around 26 GFlops of processing in under 5 watts. However we’ll be demonstrating a prototype of the 64 core processor, which will deliver a total of around 100 GFlops of processing in under 2 watts.

Prototyping boards for specialist co-processors like Epiphany can be very expensive. However through a KickStarter funded project, Parallella, boards containing a pair of ARM cores and a 16-core Epiphany processor are being made available for just $99. A “supercomputer” version of Raspberry Pi.
Biography : Dr Jeremy Bennett, an expert on hardware modeling and embedded software development founded Embecosm in 2008. Previously Dr Bennett was Vice President of ARC International plc, following their acquisition of Tenison Design where he had been CEO and CTO. Dr Bennett is author of the popular textbook, “Introduction to Compiling Techniques” (McGraw-Hill 1990, 1995, 2003) and holds an MA and PhD in Computer Science from Cambridge University.

Simon Cook has a background in low-power processors, with a particular focus on the energy constraints of code running in embedded environments. He also provides support for our work on low level binutils for both GNU and LLVM toolchains. Mr Cook is a graduate of the University of Bristol, where he achieved joint First Class Honours in Computer Science and Electronics.

Multicore Challenge Presentation

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.