Multicore Tool Demo: TVS 2014-09-16T10:18:30+00:00

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Conference: Multicore Challenge 2014 (click here to see full programme)
Session Type: Multicore Tools Demonstration
Session Title: Requirements Driven Verification in a Multicore Environment
Presenter/s: Serrie Chapman, asureSIGN Product Manager
Overview: The TVS asureSIGN tool allows users to import (hardware and software) product requirements and then ensure they have been properly verified. The demonstration will firstly cover how asureSIGN can first be used in a Requirements Driven Verification flow and then how that supports multicore product development. To demonstration will cover:

  • Requirements Driven Test and Verification
  • Combining hardware and software verification into one tool
  • Management of multicore product hardware and software requirements through to signoff
Speaker Bio: Serrie Chapman gained a degree in Computing for Real Time Systems and spent 10 years doing hardware pre-silicon testing at IP and System level with the Infineon Tricore© Microprocessor with a variety of random, directed and formal methodologies.

Serrie also spent time working in the background on work such as the IEEE1647 ‘e’ language standardization committee, supporting improvements in tracking and dissemination of information via change management, bug tracking, twiki documentation and requirements tracing.

In 2010 due to an emerging automotive safety standard ISO26262, mandating Requirements Engineering, Serrie changed roles to become the requirements manager for the Infineon Microcontroller AURIX Tricore© product family. She is involved on two EC Funding projects relating to the standard and also to emerging interoperability tooling standards, whilst also providing knowledge and expertise on Requirements engineering solutions for quality improvement and standards compliance.

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Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
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If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
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The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
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