Verification Futures is a unique one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe. This year there will be parallel tracks for the first time which will allow us to cover Hardware Verification in general and also FPGA verification.
|When:||Thursday 5 February 2015|
|Where:||Reading, UK – Holiday Inn, Wharfedale Road, Winnersh Triangle, Reading, RG41 5TS (M4 J10)|
The presentations are now available to View and Download by clicking on the links below.
The Agenda on the Day
|08:30||Registration, Coffee and Networking|
|09:25||Welcome: Mike Bartley, Test and Verification Solutions Ltd.|
“The Next Three Years …”
Cadence Design Systems. Nick Heaton (Distinguished Engineer).
|10:00||User Panel Session: Our Top Verification Challenges
“Verification IP – Trends and Technology for FPGA and ASIC Design Verification”
Mentor Graphics, Adam Rose (VIP Product Marketing Manager)
|11:05||Refreshments and Networking|
|13:00||Lunch and Networking|
“Navigating efficiently through the Verification Continuum”
Synopsys, Joerg Richter (Director R&D).
“A View of the Verification Training Market”
Doulos, John Aynsley (CTO)
|15:05||“A Cooperative Simulation Formal Methodology: Target Verification With Both Barrels.”
OneSpin Solutions, Sergio Marchese (Senior Engineer).
FPGA-based Prototyping – Tackling Large Designs Earlier
S2C Inc., Toshio Nakama (CEO)
|15:45||Refreshments and Networking|
|16:15||Vendor Panel Session: The EDA Response
– Mentor Graphics
– OneSpin Solutions
– S2C Inc.
|16:45||Meet the Sponsors in the Exhibition Area|