Verification Futures (Europe) 2015

Verification Futures is a unique one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe. This year there will be parallel tracks for the first time which will allow us to cover Hardware Verification in general and also FPGA verification.

Overview

When: Thursday 5 February 2015
Where: Reading, UK – Holiday Inn, Wharfedale Road, Winnersh Triangle, Reading, RG41 5TS (M4 J10)

Presentation Downloads

The presentations are now available to View and Download by clicking on the links below.

Presentation Title Organisation
Keynote Presentations
• The Next Three Years … Cadence Design Systems
•  Navigating efficiently through the Verification Continuum Synopsys
User Panel Session: Top Verification Challenges
•  Verification Challenges: A New ARMv8 Processor Huawei
•  Verification Challenges BluWireless Technology
•  Key Verification Challenges at Imagination Technologies Imagination Technologies
•  Predictable Verification Productivity DisplayLink (UK) Ltd.
Track #1: Hardware Verification
•  Can we train our designers to avoid bugs?
ARM Ltd.
•  Experience of using SystemC for Design and Verification BlueWireless Technologies
•  Requirements Driven Verification for Compliance
TVS
Track #2: FPGA Verification
•  Insights into the NMI FPGA Usage Survey of UK and Ireland
NMI
•  An agile development methodology for FPGA design and verification
Potential Ventures
•  Continuous integration using Jenkins in FPGA Design and verification Ericsson TV
•  Reducing the Cost of FPGA/ASIC Verification with MATLAB and Simulink MathWorks
EDA Presentations
•  Verification IP – Trends and Technology for FPGA and ASIC Design Verification Mentor Graphics
•  A View of the Verification Training Market Doulos
•  A Cooperative Simulation Formal Methodology: Target Verification With Both Barrels OneSpin Solutions
•  FPGA-based Prototyping – Tackling Large Designs Earlier S2C Inc.

The Agenda on the Day

08:30 Registration, Coffee and Networking
09:25 Welcome: Mike Bartley, Test and Verification Solutions Ltd.
09:30 Keynote Presentation
“The Next Three Years …”
Cadence Design Systems. Nick Heaton (Distinguished Engineer).
10:00 User Panel Session: Our Top Verification Challenges
Panelists:

  • Huawei, Martin Dean
    Verification Challenges: A New ARMv8 Processor
  • BluWireless, Andy Lunness
    Verification Challenges
  • Imagination, Colin McKellar (Senior Director of HW Engineering/Verification)
    Key Verification Challenges at Imagination Technologies
  • DisplayLink (UK) Ltd., Wez Davey (Lead Verification Engineer)
    Predictable Verification Productivity
10:45 EDA Presentation:
“Verification IP – Trends and Technology for FPGA and ASIC Design Verification”
Mentor Graphics, Adam Rose (VIP Product Marketing Manager)
11:05 Refreshments and Networking
Track #1: Track #2:
11:40 “Can we train our designers to avoid bugs?”
ARM Ltd., Bryan Dickman.
“Insights into the NMI FPGA Usage Survey of UK and Ireland.”
NMI, Doug Amos (FPGA Network Director).
“An agile development methodology for FPGA design and verification.”
Potential Ventures, Chris Higgs (Lead Developer).
12:10 “Experience of using SystemC for Design and Verification”
BluWireless, Andy Lunnes.
“Continuous integration using Jenkins in FPGA Design and verification.” Ericsson TV, Alan Fitch (Consultant Engineer).
12:30 “Requirements Driven Verification for Compliance”
TVS, Serrie-justine Chapman
“Reducing the Cost of FPGA/ASIC Verification with MATLAB and Simulink”
Mathworks, Graham Reith (Industry Manager: Communications, Electronics & Semiconductors).
13:00 Lunch and Networking
14:15 Keynote Presentation:
“Navigating efficiently through the Verification Continuum”
Synopsys, Joerg Richter (Director R&D).
14:45 EDA Presentation:
“A View of the Verification Training Market”
Doulos, John Aynsley (CTO)
15:05 “A Cooperative Simulation Formal Methodology: Target Verification With Both Barrels.”
OneSpin Solutions, Sergio Marchese (Senior Engineer).
15:25 EDA Presentation:
FPGA-based Prototyping – Tackling Large Designs Earlier
S2C Inc., Toshio Nakama (CEO)
15:45 Refreshments and Networking
16:15 Vendor Panel Session: The EDA Response
Panelists:
– Cadence
– Mentor Graphics
– Synopsys
– Doulos
– OneSpin Solutions
– S2C Inc.
16:45 Meet the Sponsors in the Exhibition Area
17:15 Event Closes