|Title:||Back to Basics: Understanding the Tools in Your Toolbox|
Abstract : Fifteen years ago, design engineers around the world used Verilog testbenches. Advanced engineers were building script-based random test generators and in some cases were just starting to migrate to modern verification languages such as e or Vera. We’ve come a long way in the last decade to creating a more robust infrastructure for chip verification. But are we doing what it takes to prepare for future verification challenges?
In order to move ahead, engineers today need to have a fundamental understanding of the tools in their verification toolbox. Most of us now appreciate the need to create coverage plans, use constrained random sequences, and assertion-based verification. But do we understand the reasons behind the recommendations? It has been said one must learn the rules so you know how to break them properly. Only by understanding verification fundamentals will we be able to break the current rules and move ahead towards a future with more advanced tools and techniques.
In this presentation, JL Gray, Senior Architect at Cadence Design Systems, will explore the fundamental assumptions driving today’s verification approaches, and will discuss how teams can work together to advance our ability to create quality products over the next decade.
Biography : JL Gray joined Cadence in 2013 as a Senior Architect in the IP Group. Before joining Cadence, JL was Vice President and General Manager, North America at Verilab, Inc. based in Austin, Texas. JL joined Verilab in 2004 as a pre-silicon verification consultant. He has consulted extensively in verification planning, methodology development, and project execution with a wide range of clients doing ASIC development in the US and Europe. JL has presented workshops on verification methodology and planning around the world. He has also implemented verification environments using all of the major e and SystemVerilog libraries (eRM, VMM, OVM, and UVM).
In addition to his consulting activities, JL contributed to the EDA industry as Verilab’s representative on the Accellera Verification IP Technical Subcommittee. He is also a member of the DVCon Steering Committee. JL also worked extensively on the application of social media to the EDA industry as a means of fostering collaboration in the wider engineering community. JL is well known in EDA as the author of Cool Verification, a blog about hardware verification.
Prior to joining Verilab, JL was one of the first verification engineers at ServerEngines where he created a verification environment using SystemC. He also spent 5 years at Intel, where he developed verification environments and methodologies using Specman for 1G and 10G Ethernet controllers. JL has a BSEE from Purdue University in West Lafayette, Indiana.
Presentation is unavailable at the request of Cadence Design Systems
(Due to technical difficulties we are unable to share JL’s presentation. The above link is the United Kingdom recording)