|Name:||Beatrice Brochier (FE Verification DFT Design Manager)Yassine Elkhourassani (Verification Expert)|
|Challenges:||1) Verifying Interconnect at top level covering :
2) Verifying IOMuxing in a complex SoC covering
Beatrice Brochier : Beatrice graduated from Engineering School ENSTB (EcoleNationaleSuperieure des Telecommunications de Bretagne) in 1995 and between 1995 and 1998 worked for Philips as IP designer/verifier in MPEG2 encoding for digital TV applications. In 1998 Beatrice joined VLSI technology/Philips Semiconductor company to work in Embedded Processor Group as verification and then backend engineer and then joined an internal group of Philips Semiconductors dealing with imaging coprocessor design as SoC Verification engineer in 2000. In 2003 she became design team leader of and project leader of several Soc Imaging projects until 2007. From 2007 to 2012, due to company disengagement/joint venture, was appointed as FE/Verification/DFT design manager in SoC Modem domain successively in NXP semiconductors/ST-NXP-wireless/ST-Ericsson companies.
The Sophia design team transferred to STMicroelectronics Imaging division in 2012 where she has been appointed as SoC FE/Verification DFT Design Manager.
Yassine Elkhourassani : Yassine graduated from Engineering School ENSERG, INPG Group in 2003, Grenoble and initially worked for STMicroelectronics as member of IP/SoC verification team and architecture team for interconnects performances analysis. In 2007, he joined NXP Semiconductors where he participated in successive programs for mobile phone SoCs and then moved to STEricsson as a low power design and verification specialist. Yassine currently works at STMicroelectronics/Imaging division as IP/SoC Verification Expert and is married and the proud father of two children.