|Designation:||Technical Staff Engineer|
|Title:||Get Certitude about your Tapeout Quality|
Abstract: Functional bugs are still a major contributor to chip respins. One of the main issues that cause bugs to escape during functional verification is to determine the verification quality. One of the metrics used in the past was toggle coverage at the SoC level. However, this only gives an indication that something was completely missed in verification. The paper will show how the Synopsys Certitude tool can be used to improve the quality of the SoC verification as well as how the tool can be used effectively.
Biography: Joachim studied electrical engineering at the University of Applied Sciences in Munich, focusing on Data Systems technology. He has worked for Texas Instruments, Force Computers, Motorola and now works for Freescale as Senior Staff Engineer. Joachim has presented numerous publications worldwide.