Test and Verification Solutions
|Name:||Avanish Sachan and Abhineet Sanghvi|
|Title:||ARM-based SoC Verification|
Abstract: This paper describes the ARM SoC verification using recent verification techniques like, assertion based verification, constrained random verification, formal verification and low power verification to achieve significant coverage goals in SoC level verification and reduce time to market. This paper also describes solutions and methods for various verification challenges of features like Access conflict between the shared resources, Interrupt connectivity and Priority scheme, Exception handling conflicts and priority scheme, Multiple power domain region, Clock domain crossing, Multiple reset and clock region etc
Avanish has worked on SOC and IP Level verification and has around 6.7 years of Experience in ASIC/SOC and FPGA. He has worked previously for Wipro Technologies, Freescale Semiconductor, GDA Technologies and Synplicity Software. Currently he is working in Test and Verification Solutions as a Senior Verification Engineer.
Abhineet has worked on SOC and IP Level verification and has around 6 years of Experience in ASIC/SOC verification. He has worked previously for L&T Infotech, Sasken and Intelliprop Technologies. Currently he is working in Test and Verification Solutions as a Senior Verification Engineer.