|Name:||Lavanya Rekha & Balaji Kaliraj|
|Title:||Solving Chip Level Verification Challenges|
Abstract: This paper deals with two important concepts of Design verification – Gatesims and package aware verification
Gate level simulations are very important part of verification closure, to make sure the chip is verified for functionality and dynamic timing with SDF annotated net list. For large chips with billion gates, loading the entire design in gates is next to impossible, let alone run a simulation. In our project, we address gatesims simulation issue, by functionally partitioning the design, have multiple test bench configurations, with net lists only for blocks of interest and black boxing other modules. This is to ensure every vital functionality and block interface timing are verified with comparatively smaller design. This also ensures reduced simulation time.
Another important concept is having a package aware test bench. Now adaysevery chip is deemed to work under multiple packages. Having separate verification environments for each package is an overhead. The package aware test bench works in the desired package mode, making it easy to run the test suite and verify the functionality in every package mode without disturbing the existing verification environment
Balaji Kaliraj – managing chip verification of network-switching team in Broadcom. Have Masters in VLSI Technology from NIT, Trichy and have over 12 years of experience in ASIC/FPGA verification and design. Worked with Sasken, TI and has rich expertise in base-band SoCs, network-switches.
Lavanya Rekha – MSc (Hons) Mathematics, BE (Hons) Electrical and Electronic Engineering from BITS, Pilani. Currently involved in verifying complex switches at chip-top level. Had worked with Texas Instruments, STErricsion and have about 6 years of experience in ASIC design/verification.