|Designation:||Functional Verification Specialist|
|Title:||Technology Evolution in Functional Verification: Trends, Challenges and Solutions|
Abstract: Every two years, the Wilson Research Group conducts a broad, vendor-independent survey of design verification practices around the world. Results of the just-completed survey demonstrate an ongoing convergence of SoC design practices toward a common methodology, independent of the specific tools being used. This type of methodology standardization normally drives the EDA industry into a productive wave of innovation, as EDA companies develop a variety of new tools to optimize results achieved with a standard methodology.
This session identifies the common attributes of SoC methodology that are emerging, highlights specific capability enablers for the further optimization of SoC design verification, and illustrates how Mentor Graphics’ combines advanced simulation, formal verification, and emulation technology to help you exceed your verification goals
Biography: Mark Olen is currently a Functional Verification Specialist at Mentor Graphics Corp. He has spent thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent test bench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first test bench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech’s thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Test bench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.