|Title:||Lending a ‘Formal’ Hand to CDC Verification: A Case Study of Unexpected Failure Signatures|
Abstract : Constant demand for high-performance, low-power, feature-rich devices with short time-to-market windows is the new normal in the chip design industry. Designs spend 70% of the product cycle in the hands of verification engineers who are trying to grapple with an exponential increase in the chip’s functional modes partly thanks to multiple power and clock domains. Certainly, they can benefit from some verification assistance from designers especially in areas which require a relatively deep understanding of the microarchitecture. One such niche area involves Clock Domain Crossings whose verification typically spans functional simulation, static timing analysis and gate-level simulation.
In this presentation, we identify parts of the CDC verification problem that are amenable to verification by digital design engineers and highlight cases where non-intuitive failure signatures are exposed by the use of formal analysis. We show how these failure signatures can be used to improve design quality and to bolster the verification suite. Additionally, we also discuss how the knowledge gained from this exercise can help design engineers make their designs future-proof, a much desired trait in this age of heavy design reuse. Designers lending a ‘formal’ hand to verification engineers enhances productivity, reduces product cycles and helps meet aggressive time-to-market deadlines.