Verification Futures 2014

AGENDA

Bangalore, India
Tuesday, 13 May 2014

08.30 Arrival: Networking
09.15 Introduction: Mike Bartley, Test and Verification Solutions Ltd
09.20 Panel Session: Challenge Papers – Our Top Verification Challenges

09.50 Synopsys, Amit Sharma, (Senior CAE Manager, Verification BU)
10.10 Cypress Semiconductors, Vijayabhaskar Sankaranarayanan (Senior Engineering Manager)
10.30 Refreshments and Networking
11.15 User Presentations

12.35 Jasper Design Automation
12.55 Lunch and Networking
14.10 Mentor Graphics, Ajay Goyal (Verification Technology Manager)
14.30 Texas Instruments, Vinod Paparaju (Senior Design Engineer)
14.50 Test and Verification Solutions Ltd, Gaurav Maheshwari (Engineering Manager – Software)
15.10 Refreshments and Networking
15.40 Doulos, John Aynsley (CTO)
16.00 Panel Session: The EDA response
16.45 Concluding Remarks, Mike Bartley
17.00 Meet the sponsors in the Exhibition Area
18.00 End of Conference

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