Ajay Goyal, Mentor Graphics 2014-05-26T10:05:47+00:00

Name:Ajay Goyal
Designation:Verification Technology Manager
Title:Next Generation SoC Interconnect Architectures and their Impact on Verification

Abstract: The strategy behind increasing SoC performance has transitioned from faster clock speeds to multi-core designs.  But you can aggregate several multi-core clusters while unknowingly limiting system-level performance by ignoring cache coherent interconnect functionality and performance.  This session describes two multi-core system level interconnect specifications, one optimized for mobile market designs, the other optimized for compute-intensive applications, and how they both address performance and low power system level requirements.  The presenters will also discuss the verification challenges they present, and techniques available for ensuring optimal interconnect functionality, performance, and cache coherency.

Biography: Ajay Goyal has 14+ years of experience in EDA and is working as Verification Technology Manager in Mentor Graphics. He has worked in multiple areas like Advance Verification, Emulation and System Level domain like High Level Synthesis, TLM based Design and Verification, Virtual System Platform. His areas of expertise are Emulation, Advance Verification and High Level Synthesis. He completed his BE from Nagpur University in 1999 and MBA from Symbiosis Institute of Management studies, Pune.

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.