Asiful Mondal & Vishal Goel, Texas Instruments 2014-05-29T09:34:54+00:00

Name:Asiful Mondal,  Senior Software EngineerVishal Goel,   Lead Engineer
Title:Hybrid Simulation, A SystemC – HDL Co – simulation

Abstract:  This paper is about Texas Instrument’s interest in running hybrid simulation: SystemC virtual platform integrated with RTL models. It describes why TI is interested in such an activity, how it can benefit IP design and verification as well as simulation team. The paper describes a real use case demonstration by TI, where a SystemC based simulator interacts with an IP in RTL form, all under TI’s IDE – Code Composer Studio.

Biography:

Asif has expertise in design/development of wide range of SystemC IP’s and worked on Systemc based Virtual platforms for different TI’s multi core SOC’s for 5+ years.

Vishal leads Virtual platform development team in Texas Instruments. He has led/worked on SystemC based Virtual platforms for several multi-core SOCs  in TI, focused on Video/Apps processors and Infotainment for past 10 years.

Amit Nene leads the Simulation and Modeling team in Texas Instruments. He has led/worked on SystemC based Arch Exploration and Virtual platforms for several multi-core SOCs for 10 years in TI & Infineon Technologies

Verification Futures Conference Presentation                                          Video Presentation

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.