Saravanan Mohanan, Microchip 2016-09-24T04:18:20+00:00

Name:Saravanan Mohanan
Designation:Principal Engineer
Title:Generic ABCML channel scoreboard for reuse across MOST protocols

Abstract:  Generic ABCML scoreboard is used for horizontal and vertical reuse for different automotive chips.  Scoreboard is designed for horizontal reuse across interfaces like USB, PCIE, NI, MLB & RF. scoreboard works at the block level as well as the full chip level. Scoreboard has the capability to predict packet loss and DUT packet transformation and check the same. Scoreboard has the Transaction analysis port for communicating matched packets to companion scoreboard. Scoreboard has RTL transformation prediction mode to predict the expected packet transformation done by the DUT.

Biography:  Saravanan has been in the ASIC design and verification arena for over 13 years. He has worked for different companies like Broadcom, Qualcomm, Microchip, Synopsys & Atheros communication and is currently working in Microchip. He has worked on various stages of ASIC/FPGA life cycle starting from architecture, design, synthesis, emulation and verification. He has also worked extensively in HVL’S (VERA, NTB, system verilog) and methodology ( RVM,VMM,OVM & UVM ) which includes architecting verification environments for various protocols like USB2.0 ( device , hub & OTG), PCIE ( root complex ), Ethernet (GMII,TBI,TCP,UDP,ICMP,IPV4,fragmentation/ defragmentation), I2S, SPDIF, video ( uncompressed digital video) , nand flash, 802.11.* & processor using methodology like RVM,VMM,OVM & UVM. Saravanan is passionate about almost everything he does and believes in challenging the status quo and that’s really what drives him to excel. He is also the author of the blog the Art of verification ( http://art-of-verification.blogspot.in/ )  – the blog is followed by verification engineers across the globe and listed in the VMM central site.

View the Presentation Material:

T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.