|Name:||Sukruth Pattanagiri, (Senior FPGA Engineer)Pavan Krishna, (FPGA Engineer)|
|Title:||DV flow empowerment by UVM|
Abstract: After Verilog and systemverilog, we now have UVM. With every step, the dependence of verification efforts on other languages or tools has gone down. And at the same time, the next step has usually led to increase in innovation that helped in solving complex challenges.
This presentation gives an idea of some of the components that were developed at Benu Networks, either with UVM alone or with some amount of shell scripting, and have gone a long way in reducing the human effort required in verification.
Sukruth has worked in verification for the past 9 years. He has experience in developing verification environments and flows.