Vijayabhaskar Sankaranarayanan, Cypress Semiconductors 2014-05-29T09:28:38+00:00

Name:Vijayabhaskar Sankaranarayanan
Designation:Senior Engineering Manager – Data Communication Division
Title: Verification Trends and Forms

Abstract: Shrinkage of technology nodes continue to happen as if there is no tomorrow. This kind of growth helps to pack in more functionality in a single die, but poses challenges of how to verify them. There are numerous methods of verification that comes to our help. Verification engineers need to know what to choose, where to apply it and how to apply it, to maximize the productivity benefits and minimize the total-cycle-time. This presentation addresses common confusions easing the decision making for the what-where-how problem.

Biography: 

Graduated at Madras Institute of Technology with majors in Electronics.

Graduated at Santa Clara University on Executive Development.

Spent all 15 years in Verification

Verification Futures Conference Presentation                                               Video Presentation

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