Vinod Paparaju, Texas Instruments

Name: Vinod Paparaju
Designation: Senior Design Engineer
Title:  Re-Use Of SV-UVM Based IP Verification Environment at SoC Challenges Involved

Abstract:  A typical SoC verification includes checking the integration between various components as well as simulating some of the complex use case scenarios. The latter requires a sophisticated test bench capable of driving different test patterns into the design. Developing such a bench for an SoC that has multiple sub components is no mean task. One of the noble prevalent approaches is to reuse the IP verification component at SoC. With SV-UVM fast becoming a popular environment for coverage driven verification, soon the common practice will be to reuse the SV-UVM components at the SoC level. But currently there are no guidelines defined to achieve this with minimal effort. The paper is aimed at addressing this problem. It discusses the challenges involved in reusing the IPs SV-UVM setup at SoC and defines a methodology to be followed to overcome these. Biography: Vinod Paparaju is a senior design engineer at Texas Instruments.  He has over Seven years of experience in different fields of design verification such as low power verification, Emulation verification and coverage driven verification.  He has a Master’s degree from IIT Bombay in Systems and Control.

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