|Conference:||Verification Futures 2015 (click here to see full programme)|
|Speaker:||Adam Rose, VIP Product Marketing Manager|
|Presentation Title:||Verification IP – Trends and Technology for FPGA and ASIC Design Verification|
|Abstract:||Preparing traditional VIP components can be a daunting task for a simulation or emulation testbench. This session will introduce and discuss new EZ-VIP for PCI Express that provides re-usable building blocks for common protocols and architectures for reduced testbench assembly time for FPGA design verification.
|Biography||25 yrs in electronics industry as an architect and engineering manager at Fujitsu, Motorola/Freescale, Cadence and Mentor Graphics. Main technical contributor to SystemC TLM 1.0, AVM and UVM. Currently the Product Marketing Manager for VIP within the Design and Verification Division at Mentor Graphics.|