|Conference:||Verification Futures 2015 (click here to see full programme)|
|Speaker:||Joerg Richter, Director R&D.|
|Presentation Title:||Navigating efficiently through the Verification Continuum|
|Abstract:||SoCs are growing in unprecedented complexity, employing a variety of advanced low power techniques and an increasing amount of embedded software. Advanced SoC verification teams are now driven by not only reducing functional bugs, but also by how early they can achieve software bring-up for the SoCs. This session sheds insights on Synopsys ‘ complete solution to address the verification challenges of the most advanced SoC designs, offering the highest productivity and performance, comprehensive set of software bring-up and verification technologies, and the highest performance hardware-based verification system. This session also covers how customers leverage this verification platform, for access to state-of-the-art solutions for every task in functional verification flows, from architecting a design and verification environment, to performing high-capacity, high performance static and formal applications, to achieving RTL signoff with advanced coverage closure, to address software bring-up with emulation and FPGA-based prototyping.
|Biography||Joerg Richter is an R&D Director in the Verification Group at Synopsys. He got his master degree in computer science from the University of Oldenburg, Germany. After joining Synopsys more than 18 years ago, he first worked on System Level Tools as a software engineer. After a few years he started to focus on verification and technical management. With more than decade of experience in verification he specializes in all aspects of debug for various verification technologies.|