A Cooperative Simulation Formal Methodology: Target Verification With Both Barrels
Formal techniques have become established as a key technology in the constant battle to contain spiralling verification effort. However, surprisingly only limited attention has been applied to layering formal directly into the simulation process. Leveraging the somewhat orthogonal benefits of these two approaches can significantly shorten verification cycles while improving the bug detection probability. As such, a combined, structured methodology will yield improvements. We will describe such an approach that leverages both top down verification planning and the incremental insertion of formal verification with a coverage driven methodology that enables simulation and formal to work hand-in-hand.
Close cooperation of formal and simulation that combines temporal and state-spaced verification solutions leads to rapid bug detection.
A consistent, coverage-driven methodology lies at the heart of pooling the results from the two approaches
Top down verification planning provides reliable specification coverage, but this must be tempered with incremental formal introduction for ease of deployment.
Sergio Marchese has 15 years of experience in the semiconductor industry in the areas of hardware verification and Design for Test (DFT). Marchese has worked with numerous EDA and ASIC/FPGA development companies, from large and established organizations to startups in Europe, the United States and Japan. He has held multiple positions with responsibilities in technical marketing, pre-sales support, project planning and execution. Marchese’ area of expertise is formal verification and his achievements include working with companies to incorporate formal into their verification flows, applying the technology to extremely large devices with complex components, and evangelizing the approach throughout the electronics industry. Marchese earned a Master of Science degree in Electronic Engineering from University of Catania in Italy.