Call for Submissions 2017-01-05T13:45:10+00:00

Whatever your specialty, Verification Futures provides an excellent opportunity to share your experiences and insights on the key technical and industry challenges we face in verification.

Submit an Abstract for VF2017

We are now seeking submissions for presentations and papers describing interesting and innovative experiences related to challenges faced in hardware verification. These submissions should include a brief description of the ASIC, SoC and FPGA verification challenges that need to be addresses and/or innovative solutions to improving verification. Abstracts should be targeted toward a technical audience of hardware verification engineers. Abstracts may also address the safety and security issues relating to verification.

About Verification Futures 2017

Verification Futures 2017 Europe (VF2017)is a unique one-day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe.

Key Submission Dates

Call for Submissions Opens5th February 2016
Call for Submissions Closes10th February, 2017 (or before)
Acceptance Notifications10th March 2017 (or before)
Final Presentations Required24th March 2017

Abstract Submissions

Abstract submissions should be no more than 2,500 characters and include a short biography of the speaker. All abstracts will be reviewed and notice of acceptance will be sent via email. Authors of accepted presentations must sign a copyright release form for their paper. To submit your abstract please complete the form below:

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.