Whatever your specialty, Verification Futures provides an excellent opportunity to share your experiences and insights on the key technical and industry challenges we face in verification.
Submit an Abstract for VF2017
We are now seeking submissions for presentations and papers describing interesting and innovative experiences related to challenges faced in hardware verification. These submissions should include a brief description of the ASIC, SoC and FPGA verification challenges that need to be addresses and/or innovative solutions to improving verification. Abstracts should be targeted toward a technical audience of hardware verification engineers. Abstracts may also address the safety and security issues relating to verification.
About Verification Futures 2017
Verification Futures 2017 Europe (VF2017)is a unique one-day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions. It’s also an excellent opportunity to network and catch up with other verification engineers across Europe.
Key Submission Dates
|Call for Submissions Opens||5th February 2016|
|Call for Submissions Closes||10th February, 2017 (or before)|
|Acceptance Notifications||10th March 2017 (or before)|
|Final Presentations Required||24th March 2017|
Abstract submissions should be no more than 2,500 characters and include a short biography of the speaker. All abstracts will be reviewed and notice of acceptance will be sent via email. Authors of accepted presentations must sign a copyright release form for their paper. To submit your abstract please complete the form below: