Test and Verification Solutions Ltd
|Designation:||Manager TVS France|
|Title :||Dynamic Verification of Low Power Design Intent|
Abstract : Designs today include a complex set of power reduction techniques. These techniques are increasingly making their way from the system level down to lower level design entities including IP and block level of an electronic design. These low power techniques have associated functional aspects that must be included in the functional description of the design. The related power scenarios are increasing the overall complexity of the design. Advanced methodologies and associated EDA support are needed to verify the power intent of a design. This presentation briefly addresses the verification requirements of low power design at IP level and discusses few methods and techniques to address those verification requirements.
Biography: François Cerisier has an Engineering Diploma in Digital Signal Processing from Polytech’Sophia, University of Nice-Sophia-Antipolis and over 12 years of experience in verification of IPs, CPUs and System-On-Chips and in hardware/software co-verification. François gained verification methodology expertise from industrial projects of major semiconductor companies (including Infineon, Broadcom, ST-Microelectronics, ST-Ericsson) and EDA startups. He is now leading Test and Verification Solutions subsidiary in France to provide verification services and consulting.