|Designation:||Scientist and Fellow, Synopsys.|
|Title:||Will everything start to look like a SoC|
Recent Mobile and Processor designs show remarkable similarity to each other. Consider the example of the ARM big.LITTLE configuration of A15 and A7 cores, which provide the ability to switch between high-performance and low power, or the Intel Core i7 with its mobile and desktop configurations.
With the convergence of these two previously distinct design types, the emerging result looks a lot like an SoC every time and, understandably, the largest and most complex SoCs tend to grab the headlines, but they also drive the verification agenda.
The efficiencies and capabilities of verification tools which most benefit SoC designs, are also mighty useful for other types of design, including those more typically found in European design centers, including automotive or industrial designs.
To face these challenges in the future, how will the demands of expanding scale and complexity in the midst of shrinking geometries and timescales drive advanced verification technologies into the mainstream? How quickly will ever greater use of complex Interface and bus protocols drive the adoption of Verification IP standardised around SystemVerilog? Can we continue to scale gate-level simulation or will we look to more predictive RTL simulators to find bugs earlier in the design flow? Can high-level static techniques reduce the demands on RTL simulation itself?
In fact, when we verify in the future, will everything look like a SoC?
In this presentation, Janick Bergeron, Fellow at Synopsys, spreads the verification Tarot to discern the emerging verification technologies, and how unparalleled R&D investment at Synopsys and partnership with leading practitioners is driving several unique technology breakthroughs which will overcome the verification challenges of the near future.
Janick Bergeron is a Scientist at Synopsys. He is the author of the best-selling Verification Methodology Manual for SystemVerilog and Writing Testbenches: Functional Verification of HDL Models. He is also the founder and moderator of the Verification Guild forum and writes the verification methodology blog Verification Martial Arts. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Nortel Networks. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Université du Québec, and an MBA degree granted through the University of Oregon.