|Designation:||Senior Staff Engineer, Freescale Semiconductor|
|Title:||How to improve Verification debugging using DVE|
Abstract: Today’s designs and therefore also the testbenches become more complex. The time spent to debug testbench and design issues is very high. The paper shows how the Synoposys transaction recording built into VCS® and Discovery Visualization Environment (DVE) can be used in SytemVerilog (SV) testbenches. The paper will also outline an enhanced concept on how to extend the signal based trace driver concept beyond the design border into the testbench transaction level traces
Biography: Joachim studied electrical engineering at the University of Applied Sciences in Munich, focusing on Data Systems technology. He has worked for Texas Instruments, Force Computers, Motorola and now works for Freescale as Senior Staff Engineer. Joachim has presented numerous publications worldwide.