|Title:||UVM Now or Never?|
This presentation highlights the reasons why you should (or in a few cases should not) be adopting UVM right now, and explains how using SystemVerilog with UVM to create your test benches differs from using Verilog or VHDL.
John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specialising in VHDL, SystemVerilog, and SystemC. He is co-author of the IEEE 1666-2011 SystemC standard.