Jörg Große, Breker Verification Systems Inc 2014-05-21T08:36:49+00:00

Breker Verification Systems Inc




Name:Jörg Große
Designation:Applications Engineer, Breker Verification Systems Inc.
Title:Close Your Coverage Loop with Graph-Based Scenario Models

Abstract: SoC teams rely heavily on coverage metrics as a way to gauge verification progress and determine when to tape out. With a constrained-random testbench, test plans track functional coverage closure rather than completion of explicit tests. However, there is no way to definitively close coverage. Biasing inputs, setting constraints, and simply running more tests may increase the chances of hitting coverage, but there’s no guarantee in an open-loop system. The situation is even worse at the full-SoC level, when most teams relay only simple connectivity tests and weak toggle coverage metrics.

This talk discusses the use of graph-based scenario models to both represent SoC functionality and track coverage of all functions and features. These models capture stimulus, expected results, and coverage in a single representation. This enables a true closed-loop coverage system. A verification engineer can simply point to a node of the graph, or a series of nodes that define a path through the graph, and automatically generate a self-verifying C test case that is guaranteed to cover that node or path. The result is a shorter and more predictable verification process and a SoC much more likely to work on first silicon.

Biography: Jörg Große is an Applications Engineer at Breker Verification Systems, Inc. Prior to Breker, he was an independent consultant working on automotive SoC verification and safety qualification. Previously, he was co-founder of Certess Inc., a pioneer in functional fault injection. He has also held positions in ASIC design, verification, and flow automation at Tait Electronics, Motorola, and AMD. He holds a Dipl. Ing. (FH)  from University Anhalt.

Verification Futures Conference Presentation   Video Presentation

Book you place for 2012:

The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.