Breker Verification Systems Inc
|Designation:||Applications Engineer, Breker Verification Systems Inc.|
|Title:||Close Your Coverage Loop with Graph-Based Scenario Models|
Abstract: SoC teams rely heavily on coverage metrics as a way to gauge verification progress and determine when to tape out. With a constrained-random testbench, test plans track functional coverage closure rather than completion of explicit tests. However, there is no way to definitively close coverage. Biasing inputs, setting constraints, and simply running more tests may increase the chances of hitting coverage, but there’s no guarantee in an open-loop system. The situation is even worse at the full-SoC level, when most teams relay only simple connectivity tests and weak toggle coverage metrics.
This talk discusses the use of graph-based scenario models to both represent SoC functionality and track coverage of all functions and features. These models capture stimulus, expected results, and coverage in a single representation. This enables a true closed-loop coverage system. A verification engineer can simply point to a node of the graph, or a series of nodes that define a path through the graph, and automatically generate a self-verifying C test case that is guaranteed to cover that node or path. The result is a shorter and more predictable verification process and a SoC much more likely to work on first silicon.
Biography: Jörg Große is an Applications Engineer at Breker Verification Systems, Inc. Prior to Breker, he was an independent consultant working on automotive SoC verification and safety qualification. Previously, he was co-founder of Certess Inc., a pioneer in functional fault injection. He has also held positions in ASIC design, verification, and flow automation at Tait Electronics, Motorola, and AMD. He holds a Dipl. Ing. (FH) from University Anhalt.
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