FPGA accelerated IP Validation

Conference: Verification Futures 2016 (click here to see full programme)
Speaker: Andrew Gardner (Principal Design Engineer)
Organisation: ARM
Presentation Title: FPGA accelerated IP Validation
Abstract: Simulation and Emulation don’t scale when verifying large multi-core, multi-cluster compute sub-systems. I will show how ARM utilised off-the-shelf FPGAs to construct an automated IP validation environment and why it is about more than just the hardware.

  • Payloads will determine your success or failure.
  • FPGAs are no longer black-boxes – visibility is critical to acceptance.
  • Key blockers to cycle accuracy in FPGA.
Speaker Bio: Andrew is currently responsible for the architectural specification of verification silicon and automation infrastructure.

In his previous role at ARM he led the FPGA group responsible for delivery of multi-FPGA implementations of CPU, interconnect fabric and systems IP. The primarily goal being IP validation where they built cycle-accurate systems with extensive debug features, working closely with IP validation leads and payloads groups to ensure the availability the right system configurations and test stimulus.

Slides
  • Presentations Slides: Pending
  • Video Presentation: Pending
Presentation: