|Conference:||Verification Futures 2016 (click here to see full programme)|
|Speaker:||Alex Grove (Product Specialist)|
|Presentation Title:||Using FPGAs to accelerate verification of your next ASIC: Introducing the FPGA Co-emulator|
|Abstract:||Never has the need to accelerate verification been so great; reduced market windows, ever increasing complexity and a growing need for longer tests.|
Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically known as ASIC FPGA prototyping. Such a prototype is the closest representation of the final silicon and typically used to validate and test software and perform at-speed testing of real world interfaces.
At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of such systems. These systems are very different in their capabilities to that employed for ASIC FPGA prototyping. The use of FPGAs provides the greatest capability in terms of verification cycles and are ideal for regression. With the arrival of Xilinx’s UltraScale, the capability of FPGA-based verification has never been so great.
In this short presentation we will introduce the FPGA Co-emulator and discuss two typical use cases for such a system:
|Speaker Bio:||Alex Grove has over 20 years’ experience in the EDA industry. Alex has worked for Synopsys, ARM’s EDA business unit, Synplicity, Mentor Graphics and is currently employed as an Applications Specialist at FirstEDA.|
Alex has extensive experience in the design and verification of ASICs and FPGAs, as well as a broad knowledge of the EDA industry. After graduating from Aston University, with an honours degree in Electronic Engineering & Computer Science, Alex joined Synopsys Northern Europe to work on synthesis and test.
During his time at Synplicity, Alex supported some of the most current complex FPGA designs and was a technical specialist for Synplicity’s ASIC synthesis and ASIC prototyping products.
At FirstEDA, the specialist European EDA distributor, Alex is a solutions expert on the Aldec line with a particular focus on the hardware-assisted verification and RTL simulation products.