|Conference:||Verification Futures 2016 (click here to see full programme)|
|Speaker:||Asi Lifshitz (CTO)|
|Presentation Title:||What You See Is What You Get Verification with Vtool|
|Abstract:||Functional verification is evolving slowly. Apart from being adopted across the industry, UVM technology is not a a true step forward from the 15+ years old Specman.
The next leap in functional verification has to include a higher abstraction level code-base creation. Vtool makes use of Visual Orientation and WYSIWYG concepts for better productivity and reuse.
|Speaker Bio:||Asi Lifshitz has more than 13 years of hands-on verification experience in a variety of verification projects. Mr. Lifshitz has proven experience in initiating, leading and managing verification projects. He has vast expertise in defining verification-environment architectures, infrastructures and building scalable verification environments from scratch using System-Verilog VMM and UVM. From 2011-2014 Mr. Lifshitz has managed several verification projects and tape-outs at Veriest. Previously he was a senior verification engineer at Sigma Designs. Mr. Lifshitz holds BSc and MSc in Electrical and Electronics Engineering from Tel-Aviv University, Israel.|