|Conference:||Verification Futures 2017 (click here to see full programme)|
|Speaker:||Adam Rose (Product Marketing Manager, Verification), Mentor Graphics|
|Presentation Title:||Testbench Automation|
|Abstract:||In the past two decades, the industry has converged on two complementary strategies to verify increasingly complex SoCs : the reuse of testbenches from subsystem level to SoC level, and the use of advanced verification techniques such constrained random, assertions, and verification management. The key technology that enables these two strategies is the UVM. This session will introduce three new technologies which significantly reduce the time to create a reusable testbench infrastructure for an integrated comprehensive flow that significantly improves the efficiency of the whole testbench creation process with UVM, VIP & Portable Stimulus.
|Speaker Bio:||Adam Rose is the Product Marketing Manager for Questa Verification IP. He was the author of the SystemC TLM 1.0 and the main technical contributor to the Advanced Verification Methodology (AVM), which was the first open source SystemVerilog verification methodology. He also managed the team that developed the UVM Cookbook on Verification Academy. He went on to lead Mentor’s VIP engineering team before moving into his current role.|