VF2017: RISC-V Processor Variants: Challenges and Strategies for Functional Verification 2017-07-13T09:55:52+00:00
Conference:Verification Futures 2017 (click here to see full programme)
Speaker:Marcela Zachariasova (Verification Group Leader at Codasip) Codasip
Presentation Title:RISC-V Processor Variants: Challenges and Strategies for Functional Verification
Abstract:Interest in the RISC-V Open ISA has grown incredibly quickly – it is clearly something that the semiconductor industry needs and has been waiting for. Advantages for design teams are somewhat similar to those provided by Linux in the OS domain: flexibility built on a set of basic standards and a sustainable, growing ecosystem. Hence, an overall reduction in cost and effort, as well as a wide range of function/power/performance variants. But what about verification? This activity is generally held to take over half of a design team’s time.

RISC-V verification becomes a challenge when the particular functionality-performance combination that I want is not available off the shelf. In these circumstances, someone has to produce a variant of the design (RTL + Software Development Kit (SDK)) and verify it. This is clearly a challenge for RISC-V providers, whether they be Silicon IP (SIP) companies or service organisations within large companies. It should be a concern for all RISC-V users, since they want bug-free cores with a cost/performance ratio as low as possible.

In this paper, we share some of our combined experiences in this area – our companies, Codasip and TVS, have been tackling the issues mentioned from the points of view of a SIP provider, a tools supplier and a verification services consultancy.

  • RISC-V verification becomes a challenge when the particular functionality-performance combination that I want is not available off the shelf.
  • A highly automated processor design flow can greatly reduce verification effort.
  • In the case of a well-defined, highly-reused architecture such as RISC-V, additional automation that drives microarchitecture implementation from an ISA-level description further facilitates verification.
Speaker Bio:Marcela Zachariasova is currently a Verification Group Leader at Codasip, Brno (Czech Republic) and Assistant Professor at Brno University of Technology (Czech Republic). She has a broad experience in the field of hardware design and verification, she has successfully worked on multiple network FPGA-based accelerators, processors and complex SoCs. Her team is focused on verification of application-specific processors developed by Codasip, while two of these processors are currently based on popular RISC-V specification from Berkley.
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