Alternative Formal techniques to increase Verification productivity

Formal verification techniques such as property checking and formal applications have become an important part of today’s verification methodology. Designers play an increasing role in verification, both because of the additional resource and, also, because of the cost effectiveness of finding bugs earlier in the design flow.

As we look for greater increases in productivity, we need to look for optimal formal techniques to address the practical challenges of the entire design and verification team.

This presentation considers how the practical challenges of design bring-up, rapid verification of iterative design refinement, root cause analysis and verification sign-off can be addressed with transactional equivalence checking, sequential equivalence checking and formal debug techniques.

  • Transactional equivalence checking helps find bugs for quick design bring-up, verifies iterative design changes and provides a technique for verification sign-off.
  • Sequential equivalence checking can verify iterative manual RTL edits such as clock gating, data gating, register retiming, and DFT insertion.
  • Formal techniques can augment root cause analysis in debug.

Hear the above talk by Doug Fisher, Senior Staff Application Consultant at Synopsys, and 8 other speakers at the free one day Formal Verification conference held at Reading, UK on Thursday, 21 May and you have the option to attend in person or via remote access. Attendees will gain from the event whether they are just trying to learn how to apply formal verification or expert users.

Places are limited and this event often sells out so we recommend early registration.

Speaker and registration details can be found here.

2015-05-18T05:17:38+00:00 18th May, 2015|Active Event, Blog, Events|
T&VS NEWSLETTER SIGN-UP
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
DOWNLOAD REQUEST
Please complete the following form and then click 'submit' to gain access to the download.
FREE QA ASSESSMENTS
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.