Alternative Formal techniques to increase Verification productivity

Formal verification techniques such as property checking and formal applications have become an important part of today’s verification methodology. Designers play an increasing role in verification, both because of the additional resource and, also, because of the cost effectiveness of finding bugs earlier in the design flow.

As we look for greater increases in productivity, we need to look for optimal formal techniques to address the practical challenges of the entire design and verification team.

This presentation considers how the practical challenges of design bring-up, rapid verification of iterative design refinement, root cause analysis and verification sign-off can be addressed with transactional equivalence checking, sequential equivalence checking and formal debug techniques.

  • Transactional equivalence checking helps find bugs for quick design bring-up, verifies iterative design changes and provides a technique for verification sign-off.
  • Sequential equivalence checking can verify iterative manual RTL edits such as clock gating, data gating, register retiming, and DFT insertion.
  • Formal techniques can augment root cause analysis in debug.

Hear the above talk by Doug Fisher, Senior Staff Application Consultant at Synopsys, and 8 other speakers at the free one day Formal Verification conference held at Reading, UK on Thursday, 21 May and you have the option to attend in person or via remote access. Attendees will gain from the event whether they are just trying to learn how to apply formal verification or expert users.

Places are limited and this event often sells out so we recommend early registration.

Speaker and registration details can be found here.