Bring IP Verification Closure to SoC

“To cater to exponentially growing complexity and ever shrinking ‘Time to Market’, we need to find better ways to achieve our verification goals faster.” states Gaurav Gupta (Staff Design Engineer) Freescale Semiconductor Inc. at his forthcoming talk at DVClub Europe on Tuesday 1st December.

In this presentation Gaurav will explain that the distinction between IP and SoC verification is getting obscured as the dynamics of verification shift to a ‘Sub-System’ containing multiple IPs working together.

There is a clear need to make SoC verification and IP verification more ’inter-reusable’ in-order to mitigate not just the issues in modelling of environments around Standalone IPs versus actual SoC/Sub-System but also to empower system level verification environment with scalable and re-usable methodology which defines guidelines about how to handle and manage verification problems efficiently in structured manner.

It would be desirable to not just be able to port stimulus from IP verification environment to a SoC verification environment but to have SoC environment an extension of the IP verification environment.

See the full agenda and registration details here

About DVClub

The principal goal of DVClub Europe is to have fun while helping build the verification community through regular educational and networking events.  Attendance is free and can be in-person by attending one of three European venues or via remote access.  Attendance is open to all non-service provider semiconductor professionals but registration is essential as these sessions are often over-subscribed.  DVClub Europe is coordinated by TVS with the support from a number of sponsors.