Bring IP Verification Closure to SoC

Gaurav Gupta, Staff Design Engineer at Freescale Semiconductor Inc,will be at DVClub Europe on1st December to discuss the Scalable methods to bridge the gap between IP and SoC Verification.

There is a clear need to make SoC verification and IP verification more ’inter-reusable’ in-order to mitigate not just the issues in modelling of environments around Standalone IPs versus actual SoC/Sub-System but also to empower system level verification environment with scalable and re-usable methodology which defines guidelines about how to handle and manage verification problems efficiently in structured manner.

If you are working on “IP and SoC Verification“ or wish to get yourself acquainted with the latest in IP Verification Closure, this session is a must attend.

Attending the DVClub conference on December 1stis free but places are limited so we recommend early registration.

You can register  here

2015-11-26T07:16:57+00:0026th November, 2015|Active Event, Blog, Events|