Co-Verification for Complex SOC Designs at DVClub Bangalore, 9 APR 15

DVClub brings together technology users, developers and industry experts to network, share best practices on critical design and verification issues. DVClub is a unique platform to discuss trends and explore challenges in design and verification.

This time around ChristDas from TVS, Singapore will be discussing on the topic “Co-Verification for Complex SOC Designs” at Cadence office , Ecospace , Bangalore from 9:30 AM to 12:30 PM and pre – registration is required.

Co-verification is helpful to tackle growing SOC Design complexity and associated SW development, thereby reducing the time-to-market delays.

Software content of electronic products is increasing exponentially and is most often the pacing item for product completion.
Software simulation alone is not fast enough to test the volume of software being written for today’s electronic products. Using acceleration and emulation for hardware/software co-verification takes advantage of the investment made in the emulator for SoC  verification to speed software debugging thus shortening product cycles by several months.

Register Here.

2015-04-07T10:50:09+00:00 2nd April, 2015|Active Event, Blog, Events|
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.