DVCon Europe opens call for Papers and Tutorials

I think we can confidently declare DVCon Europe 2014 a success! With 245 attendees from 83 different companies attending 14 tutorials and 27 papers, the numbers look good.

We are now planning DVCon Europe 2015 for November 11th and 12th in Munich, and you have a chance to contribute with a paper or a tutorial with the call for both now open. According to Martin Barnasconi, General Chair DVCon Europe,“The tutorials at DVCon Europe target technical deep-dives into practical design and verification topics, to educate the audience by sharing knowledge and real-world examples. We welcome submissions of individuals and companies to contribute to this learning experience at DVCon Europe”.

Tutorials are typically 90 minutes in length and should cover one of the following topics

  • Electronic System Level (ESL) design.
  • SystemC (or more generally, C/C++ based) for design, verification and/or high level synthesis.
  • Hardware/software co-design or and co-verification, acceleration or emulation.
  • Mixed-signal design and verification using SystemC-AMS, Verilog-AMS, VHDL-AMS, etc.
  • Using SystemVerilog and/or the Universal Verification Methodology (UVM) for functional and coverage-driven verification.
  • Verification and validation methodologies, verification management and/or traceability.
  • Assertion-based Verification (e.g., SystemVerilog Assertions, PSL, etc.)
  • Low-power design techniques using standards like UPF, CPF, IEEE1801, etc.
  • Design or verification for functional safety (e.g., ISO 26262, DO-254)

So plenty to choose from and, of course, you could collaborate with a colleague or partner organisation. Papers are also invited on similar topics. In 2014 TVS presented a popular tutorial on Requirements Driven Verification.This year I will be looking after the poster session and selecting potential posters from the paper submissions. So if you submit a proposal for a paper you could potentially be selected as a poster.

Alternatively, you could just attend. We asked 2014 delegates “What are the main reasons for your attendance at DVCon Europe?” and the reasons are varied as depicted in the figure.

image

A number of attendees mention visiting EDA vendors and learning about new tool developments and with 19 Exhibitors in 2014 they were not disappointed. You can expect more exhibitors in 2015.

So, mark November 11th and 12th in your diary as “Attending DVCon Europe 2015”.

Read more in the website.

2015-04-08T08:04:01+00:00 7th April, 2015|Active Event, Blog, Events|
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