See T&VS at DVCon USA (Feb 26 – Mar 1, 2018) and on Panel: Can we learn anything from new big data techniques?

During the last week of February, the DoubleTree hotel in San Jose, California will once again host DVCon U.S. and T&VS are delighted to be contributing to the ‘Big Data’ panel discussion titled: Help! System Coverage is a Big Data Problem! moderated by Brian Bailey of Semiconductor Engineering.

Portable Test and Stimulus – The Next Level of Verification Productivity is Here” and throughout the conference to discuss our Portable Stimulus Services , including the recently announced cooperation with Cadence that leverages our years of experience designing re-usable verification IP to help their customers with the adoption and effective use of the Cadence Perspec System Verifier tools. Read More

DVCon U.S. 2018 At-A-Glance

  • February 26 – March 1, 2018
  • DoubleTree Hotel, San Jose, CA
  • Website: https://dvcon.org/

Panel: Help! System Coverage is a Big Data Problem!

Each panelist, including Mike Bartley, founder and CEO at T&VS, will give a short positioning statement to kick things off, which will be followed by some lively discussion amongst the panelists and a Q&A session with the audience.  The T&VS position is that:

  • Suddenly everything is “big data”.  Our problem hasn’t changed – we need to analyse messy data from several sources to predict an end date and make a binary tape-out decision.  Can we learn anything from new big data techniques? Mike Bartley, founder and CEO at T&VS

Panel Summary: While coverage is undergoing a renaissance, partly driven by new automotive systematic verification methodologies that demand a rigorous approach to measuring system coverage versus original specification, more attention to system coverage is needed. Coverage metrics help development groups understand the quality of their verification efforts and coverage holes represent risk of failure. At the system level, there are no standardized metrics and no way to exhaustively close coverage. The emergence of Portable Stimulus brings some structure to the problem, but opens up as many questions as it provides answers. For a typical design, the total number of paths through a graph is on the order of 2100 and that’s before all the possible concurrency issues are considered. System coverage has all of the hallmarks of being a big data problem. The good news is that system coverage is directly tied to intent and development groups soon will have better quality metrics than they did in the past. Moderator Brian Bailey and a panel of experts will explore various best practices in use by the industry. They will examine ways in which Portable Stimulus, formal verification methods, emulation and prototyping can be used to help provide the necessary confidence.

  • Wednesday February 28, 2018
  • 8:30am – 9:30am
  • Room: Oak/Fir
  • Moderator: Brian Bailey of Semiconductor Engineering
  • Panelists: Mike Bartley (Test and Verification Solutions), Vigyan Singhal (Oski Technology, Inc.), Mark Glasser (Nvidia Corp.), Adnan Hamid (Breker Verification Systems, Inc.) and Ashish Darbari (Axiomise Ltd.)
  • Organisers: Maheen Hamid and Dave Kelf (Breker Verification Systems, Inc.)

Arrange a Meeting

If you would like to arrange to meet-up with the T&VS team at DVCon for an informal chat about your next verification project please Contact Us to arrange a suitable date and time, or simply call one of our local offices.

A Word from the DVCon 2018 Chair

“I am very proud of the program we have put together for our attendees at DVCon this year. It is the must-attend conference for design and verification engineers because it continues to grow and evolve with the needs of industry. This year we’ve added some new vertical topic areas that I think attendees will find particularly intriguing and useful. Safety critical verification is a theme that attendees will see addressed throughout the conference, and the tutorials on Thursday afternoon are focused primarily on issues surrounding automotive safety and compliance. There is also a paper that will discuss UVM-based Verification of a RISC-V Processor Core. There is something for everyone at DVCon and our team of reviewers has done an excellent job of pulling the best for the program from an outstanding group of proposals.”

Tom Fitzpatrick, Program Chair

2018-02-21T12:37:57+00:00 8th February, 2018|Events, Hardware Verification, Thought Leadership|
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