Encapsulating Concurrent Assertions in UVM

IP/SoC checks are very important in any verification activity. But class-based system verilog used in UVM does not allow concurrent assertions. Thus, in order to implement concurrent assertions, we require non-class based objects like interfaces. But this creates problems of encapsulation and isolation.

Surinder Sood of SanDisk presented some pragmatic approaches for encapsulation and operation of assertions including mechanisms to make assertions aware of UVM Phases of the class-based environment at the DVClub India Conference-“IP Verification Challenges” on 11 May 2016.

You can view the slides& recordings here

2016-05-23T07:09:51+00:0023rd May, 2016|Active Event, Blog, Events|