FPGA accelerated IP Validation

Andrew Gardner, Principal Design Engineer at ARM, discussed how ARM utilized off-the-shelf FPGAs to construct an automated IP validation environment and why it is about more than just the hardware in Verification Futures Conference organized by T&VS.

The Presentation Slides of “FPGA accelerated IP Validation” are available now

2016-02-10T07:26:39+00:0010th February, 2016|Active Event, Blog, Events|