FPGA accelerated IP Validation

Simulation and Emulation don’t scale when verifying large multi-core, multi-cluster compute sub-systems. Andrew Gardner, Principal Design Engineer at ARM, discussed how ARM utilized off-the-shelf FPGAs to construct an automated IP validation environment and why it is about more than just the hardware in Verification Futures Conference which took place on 4 February 2016.

You can view the slides and presentations here

2016-02-22T12:30:20+00:0022nd February, 2016|Active Event, Blog, Events|