Is Hybrid simulation the panacea for Verification problems?

High simulation times have for long been a bottleneck in functional verification.  Over the years, different techniques have evolved to counter this problem some of which incorporate expensive hardware to replicate Silicon run times.

One of the innovative solutions to have emerged is Hybrid Simulation – a technique to simulate components at different levels of abstraction concurrently.  In addition to drastically reducing simulation times, hybrid simulation offers other advantages as well – accelerated pre-Silicon software development, more efficient IP Verification and system level improvements.

If you are interested in knowing more about this technique, you should surely register for the Verification Futures Conference at Hotel Park Plaza, Marathahalli, Bangalore on April 16th.  Vishal and Asif from Texas Instruments and Bharat from Test and Verification Solutions will present a user paper on Hybrid Simulation.  In addition to detailing how Hybrid Simulation can reduce simulation run times, the paper will highlight how IP design and verification teams can benefit from this approach.  The paper will also cover a real use case demonstration by TI, where a SystemC based simulator interacts with an IP in RTL form, all under TI’s IDE – Code Composer Studio.

Delegates from Intel, Qualcomm, LSI, Broadcom, Mentor Graphics, Synopsys and many others have already registered for Verification Futures Conference.  Make sure you do not miss out on this opportunity to learn more about how top companies are overcoming their verification challenges.  Registration is free and includes lunch and refreshments.

Speaker slots for User and Challenge paper slots at the conference are filling fast and if you would like to present on your experiences in verification, we urge you to contact us as soon as possible.

On 16th April, 2014, all roads lead to the Verification Futures Conference.  Say goodbye to your Verification problems once and for all!

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