In the next DVClub Europe, Monday, 7th July, Gaurav Jain, Senior Design Engineer from Freescale Semiconductor, will present a case study on the deployment of System Verilog low power assertions along with CPF enabled dynamic simulations to verify a Next Generation Low Power SoC. and how multiple assertion categories were deployed to target verification of low power design features, Integration of Macro models, sequencing and connectivity of critical control signals and to prove the clocking and reset schemes in each device mode.
Why not join us at one of our locations in Bristol, Cambridge, Eindhoven, Grenoble and Sophia Antipolis to hear the full presentation from Gaurav. We will also be joined by speakers from ARM, Mentor Graphics and Synopsys and promises to be an interesting and informative afternoon. If you are unable to attend one of our locations, why not register for Remote Access?