Next Generation SoC Interconnect Architectures

The Impact of Next Generation SoC Interconnect Architectures on Verification

Strategies to increase SoC performance have transitioned from faster clock speeds to multi-core designs and this presents many new verification challenges. At Verification Futures Bangalore on May 13th, Ajay Goyal,Verification technology Manager at Mentor Graphics, will present on the verification challenges for two multi-core system level interconnect specifications – one optimized for mobile market designs and the other optimized for computer-intensive applications. Ajay’s presentation will address the verification risks emerging from aggregating several multi-core clusters such as verifying cache coherent interconnects functionality.

With speakers from ARM, Synopsys,Texas Instruments, Jasper Design Automation, Mentor Graphics, Doulos, Benu Networks, Omniphy and T&VS presenting on a diverse range of verification topics like Hybrid Co-simulation, Low Power Verification of ARM CPU Sub-System using IEEE 1801, ABCML scoreboard design for reuse across MOST protocols etc, prototyping and AMS challenges,Verification Futures is an event no DV professional can afford to miss!

The registration count is rapidly approaching the 450 mark. Feel free to forward this to your colleagues too. For those who cannot attend in person, we are accepting webinar registrations too!

2015-01-19T11:41:37+00:0029th April, 2014|Events, Hardware Verification, TVS-India|