Predictable verification productivity

Wez Davey highlighted the key challenges in achieving predictable verification productivity in DisplayLink’s IC development process. Wez identified three key points to achieving this: getting even greater re-use of FPGA and simulation platforms within multiple discipline teams; spending less time fixing RTL and testbench bugs; and spending less time fixing bugs in third party tools, IP and VIP.

Click here to see the presentation.

2015-02-12T07:50:31+00:0012th February, 2015|Active Event, Blog, Events|