Real Value Modelling for Improving the Verification Performance

Due to increasing unpredictability and complexity of systems, circuit SPICE and Fast SPICE simulation cannot deliver verification closure on time. With the demand to have more functionality in today’s designs, the high performance SoC’s should further accommodate Analog and Mixed Signal (AMS) designs. This leads to growing necessity of methodology for accurate and fast verification of AMS designs.

Mallikarjuna Reddy from Test and Verification Solutions and Venkatramana rao from Mindlance Technologies, presented on how to improve the verification performance using real value modelling at the DVClub Europe Conference-“Verifying Analog and Physical Designs”, on 12 September 2017.

You can view the slides and presentations here