SoC Design Verification using 3rd party IPs – Challenges & Guidelines

At DVClub Bangalore on 18 June 2015, Vedantham and Prem C K, Members of Technical Staff, AMD are presenting their experiences in using 3rd party IPs for SoC Design Verification.

This presentation will cover important considerations from Verification planning to pre-silicon through tape-out. It will also provide a few guidelines that would help to address the issues that may potentially compromise the verification quality.

Their presentation will focus on the following Key Points:

  • Interoperability of Vendor IPs.
  • Test planning considerations.
  • Coverage planning considerations.

Vedantham has 14+ years of work experience in multimillion gates ASIC/SOC functional verification. He is familiar with standard ASIC design flow from design concept to tape-outand has participated in many multi-million gate SOC tape-outs .

Prem C K has 15+ years of Verification work experience on IP, Sub-System and System Level and has hands on Experience in Pre and Post silicon Validation.

  • Attending the DVClub conference on June 18is free but places are limited so we recommend early registration.

You can register here

2015-06-15T05:44:47+00:0015th June, 2015|Active Event, Blog, Events|