Static Power Intent Verification of Power State Switching Expressions

Low power architecture of a design (specified in terms of UPF/CPF) goes through a series of refinements throughout the design cycle.Therefore it is very crucial to check whether the initial low power intent remains intact in these refinement steps.

Any erroneous refinement step usually leads to functional bugs in the design, which can only be detected late in the verification cycle.

Srobona Mitra of Synopsys will discuss a static checking methodology for verifying early that the power state switching expressions in a power architecture specification are equivalent through successive stages of power intent refinement at DVClub Europe on 22 September 2015.

  • Attending the DVClub conference on September 22nd is free but places are limited so we recommend early registration.You can register here