SystemC-based UVM verification infrastructure

BluWireless designs use SystemC and so it was a natural choice to also select SystemC for the test bench language. However, they also wanted to follow current industry best practise with a UVM-compliant verification strategy. In this talk at Verification Futures Andy Lunnessof BluWireless will outline the development of a SystemC testbench that is UVM compliant with a TLM 2.0 interface

Verification Futures, held on February 5th in Reading and online, is a unique free one day conference, exhibition and industry networking event organised by TVS to discuss the challenges faced in hardware verification. The event gives the opportunity for end users to define their current and future verification challenges and collaborate with the vendors to create solutions.

Register here.

2015-08-03T10:11:40+00:003rd February, 2015|Active Event, Blog, Events, SystemC|