T&VS announces new CPU Verification tool development

T&VS is pleased to announce the development of a new “Event Stream Generator”.

Processors (CPU, GPU, DSP, etc.) are becoming more complex and require more verification. The current best practise in processor verification is instruction stream generation.

The T&VS instruction stream generator (asureISG) will have the following major features

  • Offline generation: the instructions are generated in advance of simulation for quicker generation speeds.
  • Sequence generation: sequences of instructions can push a design into the corners where the bugs lurk!
  • Multicore support: asureISG can be programmed to generation instructions for multiple cores allowing it to generate sequences of instruction streams for multiple cores. Those sequences can interlaced with defined synchronisation points for multicore verification.
  • Coverage support: coverage models can be built into the generation to help direct the generation.

asureISG is currently under development with T&VS key clients but we are open to more early adopter partners who want to influence the development.

Contact Mike Bartley for more information.

2017-05-10T07:14:54+00:00 23rd February, 2015|Active Event, Blog, Events|
The T&VS newsletters inform you about industry news, events and information from T&VS. No spam, we promise and it is always easy to unsubscribe.
We never share your information. Read our Privacy Statement
Interested in Formal Verification?
Then why not attend the TVS Formal
Verification Bootcamp training?
The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.
Bootcamp Enquiry Form
If you are interested in receiving additional information on the course then simply email Mike Bartley (TVS CEO and Course Leader) by entering your details below.
Interested in SystemC?
FREE SystemC UVM Library Now Available
The TVS SystemC UVM library closely mimics UVM but gives users a license free UVM-based verification environment.
Have your product requirements been successfully tested and implemented?
Find out how asureSIGN can help you implement a successful Requirements Driven Verification and Test Strategy by visiting asureSIGN or enter your details and we will be in touch.
Course Dates and Pricing
To receive additional information, including course dates and pricing, please contact our training team who will be happy to help.
Download Request
Please complete the following form then click 'submit' to access the download.
Presentation Request
Please complete the following form then click 'submit' to gain access to the presentations.
Please complete the following form and then click 'submit' to gain access to the download.
Did you get what you were looking?

Let the testing experts help. We will run a FREE QA assessment which will include our top 5 recommendations to help maximise your testing.