T&VS is presenting on M-PHY Analog Modelling and Verification at DVCon India

At DVCon India Mallikarjuna Reddy, Venkatramana Rao and Somanatha Shetty from T&VS are presenting on ‘M-PHY Analog blocks Modelling and Verification using SV/UVM-MS’.

In this presentation, T&VS explore how application of advanced AMS modelling techniques help in minimizing the run time significantly for mixed signal designs .T&VS also present benefits of developing SV/UVM-MS environment for verifying stand-alone M-PHY analog top and end-to-end M-PHY feature verification.

If you are working on M-PHY Verification or wish to get yourself acquainted with the latest in AMS Verification, this session is a must attend. Reserve your slot for the D2A2.3-DVsession at Sitara now!

2015-09-07T07:22:34+00:007th September, 2015|Active Event, Blog, Events|